As one of the scaling techniques for increasing the density of semiconductor devices, a multi-gate transistor has been suggested. The multi-gate transistor is obtained by forming a fin or nanowire-shaped multi-channel active pattern (or silicon body) on a substrate and forming gates on the surface of the multi-channel active pattern.
As the feature size of metal oxide semiconductor (MOS) transistors is reduced, a gate and a channel formed under the gate are becoming shorter in length. The reduced length of the channel increases the scattering of electric charges and reduces the mobility of the electric charges in the channel. The reduced mobility of the electric charges can be an obstacle to improving a saturation current of a transistor.
Therefore, various researches are being conducted to increase the mobility of electric charges in a transistor with a reduced channel length.